IJEEDC Design of High Speed Cryptography using Finite Field Multiplier

Journal Paper

Paper Title :Design of High Speed Cryptography using Finite Field Multiplier

Author :Sharon Rebba, S. Thirumala Devi

Article Citation :Sharon Rebba ,S. Thirumala Devi , (2017 ) " Design of High Speed Cryptography using Finite Field Multiplier " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 42-44, Volume-5,Issue-8

Abstract : The process to develop a federal information processing standard for the advanced encryption algorithm to replace the data encryption standard. In this project, we proposed an efficient VLSI architecture for advanced encryption standard design methodology in order to provide a high-speed and effective cryptographic operation. High-performance and fast implementation of proposed multiplication is applied to cryptographic systems. The internal multiplier consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In this paper, we propose efficient and high speed architectures to implement cryptography using proposed multiplier. Cryptography is the operation in wireless communication between transmissions and receiving of data, the secured data is communicated in an unsecured channel between transmitter and receiver with high security. At the transmitter side the original data is converted in to secured sequence and at the receiver side the secured sequence is converted in to original data sequence.

Type : Research paper

Published : Volume-5,Issue-8


	\|		PDF	\|	Viewed - 70	\|	Published on 2017-10-21

Jan. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	141
Paper Published	:	1771
No. of Authors	:	4924

Published : Volume-5,Issue-8

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