Paper Title :Capacity Enhancement Of Short Circuit Laboratory Using Parallel Operation Of Transformer
Author :Tejpal Purohit, H. K. Mishra, Hemang Pandya
Article Citation :Tejpal Purohit ,H. K. Mishra ,Hemang Pandya ,
(2014 ) " Capacity Enhancement Of Short Circuit Laboratory Using Parallel Operation Of Transformer " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 48-53,
Volume-2,Issue-5
Abstract : Abstract—Since capacity of short circuit (S.C.) laboratory depends upon effective impedance of testing transformer and line
connecting to the test equipment, which is designed to the optimal level while developing the S.C. Lab but still its fault level
is lower. To test higher rating of transformer, a high testing fault level is required. Paralleling of S.C. testing transformer is
the only effective way to reduce the effective impedance and increase fault level of the S.C. Lab. Percentage impedance of
the conventional power transformer are found to be rated at 7 to 8% , while in case of S.C. testing transformer. This is much
lower. S.C. testing transformer is specially designed transformer due to above aspect. This paper targets to provide solution
for enhancing S.C. capacity of testing laboratory by connecting another transformer of similar capacity parallel to existing
one and to deal with the phenomena of sympathetic inrush current, circulating current etc. This paper discusses simulation in
ETAP & PSCAD for fault current estimation for the single S.C. testing transformer and after paralleling of two transformers.
Simulation results and mathematical results both are observed identical
Type : Research paper
Published : Volume-2,Issue-5
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-702
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Copyright: © Institute of Research and Journals
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Published on 2014-05-14 |
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