Paper Title :Design of 9-Tap Fir Filter Using High Speed Low Power Vedic Reversible Multiplier
Author :Manoj Kumar.K, Mithun Kumar Shetty H, Meghana Kulkarni
Article Citation :Manoj Kumar.K ,Mithun Kumar Shetty H ,Meghana Kulkarni ,
(2016 ) " Design of 9-Tap Fir Filter Using High Speed Low Power Vedic Reversible Multiplier " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 53-57,
Volume-4,Issue-11
Abstract : The area, power dissipation, speed, cost etc are the real challenges of the VLSI outline. In this paper, we have
designed a 9-Tap FIR filter using Vedic reversible multiplier. The design is explicitly focused on achieving more speed and
less power dissipation. The multipliers utilize the most important part of the computation in any arithmetic operation of
CPU. Here we designed a multiplier concentrated on the speed and the power dissipation. The speed of the multiplier is
increased by designing it with a concept called Vedic mathematics. Vedic mathematics consists of 16 sutras (algorithms), out
of which Urdhva Tiryakbhyam (UT) sutras is used for multiplication. Hand in hand with speed, power reduction is also
important. We have used a technique called reversible logic with which Vedic multipliers can be implemented. The
combination of reversible logic and Vedic multiplier turns into a perfect system where both low power and speed can be
achieved. The proposed digital 9-Tap FIR filter is coded using verilog language and the performance of the design is
evaluated and synthesized using Xilinx 13.1 synthesis tool.
Index Terms- Finite Impulse Response (FIR) Filter, Urdhva Tiryakbhayam (UT), Vedic Multiplier, Reversible Logic,
Quantum Cost.
Type : Research paper
Published : Volume-4,Issue-11
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-6291
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Copyright: © Institute of Research and Journals
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Published on 2016-12-16 |
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