Paper Title :Review On Universal Verification Methodology (UVM) Concepts For Functional Verification

Author :Siddharth Raghuvanshi, Viswajeet Singh

Article Citation :Siddharth Raghuvanshi ,Viswajeet Singh , (2014 ) " Review On Universal Verification Methodology (UVM) Concepts For Functional Verification " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 101-107, Volume-2,Issue-3

Abstract : Abstract- The main goal of functional verification in hardware design is to find out the bugs in design description given by design engineers and to check the functionality of design whether the output matches with desired value or not and then customize the design to get the desired functionality of DUT. Various verification techniques have been developed from past few years to make the verification process much easier and user friendly. This paper presents a recent approach to using UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is to identify a minimal set of concepts sufficient for constrained random coverage-driven verification in order to ease the learning experience for engineers coming from a hardware design background who do not have extensive object-oriented programming skills. We describe coding guidelines to address the canonical structure of UVM component and transaction, the construction of the UVM component hierarchy, the interface with the design-under-test, the use of sequences, and the use of the factory and configuration mechanisms. We also provide some key factors which allowed the user to migrate from OVM to UVM for verification purpose.

Type : Research paper

Published : Volume-2,Issue-3

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