International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Jul. 2024
Submitted Papers : 80
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  Journal Paper

Paper Title :
Performance Analysis Of Parallel Prefix Adder

Author :Manjunatha Naik V, Poornima N

Article Citation :Manjunatha Naik V ,Poornima N , (2015 ) " Performance Analysis Of Parallel Prefix Adder " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 74-77, Volume-3, Issue-7

Abstract : Addition is important in many of data path subsystems. The primary factor for any design is to reduce the power dissipation and to increase the performance. To achieve the performance and to reduce the power dissipation, selection of adder topology is an important thing. The use of parallel prefix adders (PPA’s) increases the performance by reducing the power dissipation. This paper represents the comparison between the different prefix trees and the implementation of radix- 4, 32 bit parallel prefix adder with sparseness of 4. The work involves the implementation of radix-2 and radix-4 32 bit parallel prefix adder structures by comparing power, delay, power delay product and number of computational nodes. The comparison result reveals that radix-4, 32 bit parallel prefix adder realizes minimum power and delay. The power and delay of both the adders are analyzed and compared. Cadence sim vision tool used for verilog implementation and Cadence virtuoso tool used for schematic implementation and the Encounter tool is used for the physical design of the both the adders. Keywords —Parallel prefix adders, arithmetic and logic unit, Power delay product.

Type : Research paper

Published : Volume-3, Issue-7

DOI - 10.18479/ijeedc/2015/v3i7/48267

Copyright: © Institute of Research and Journals

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