Paper Title :Improved Analytical Modeling For Junctionless Transistor

Author :Vikkee, Ashutosh Nandi

Article Citation :Vikkee ,Ashutosh Nandi , (2015 ) " Improved Analytical Modeling For Junctionless Transistor " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 42-44, Volume-3, Issue-7

Abstract : In this paper, we have derived and proposed an analytical model of junctionless transistor by solving poisson equation with variable separation method. The 2-D poisson equation in both silicon and oxide regions are solved to deduce expressions of surface potential, threshold voltage and drain induced barrier lowering of double gate junctionless transistor. Behavior of Derived expression is compare with analytical model of junctionless DG-MOSFET and TCAD sentaurus results. Proposed results give good agreement with these results. Index Terms- Junctionless transistor, 2-D poisson equation, surface potential, Short channel effect (SCE), Drain Induced Barrier Lowering (DIBL).

Type : Research paper

Published : Volume-3, Issue-7

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