IJEEDC FPGA Implementation of Fault Tolerant Subtractor Using Verilog for High Speed VLSI Architectures

Journal Paper

Paper Title :FPGA Implementation of Fault Tolerant Subtractor Using Verilog for High Speed VLSI Architectures

Author :Suba Lakshmi R, Karlyn Cynthia F M, Vaishnavi R, Gayathri G

Article Citation :Suba Lakshmi R ,Karlyn Cynthia F M ,Vaishnavi R ,Gayathri G , (2024 ) " FPGA Implementation of Fault Tolerant Subtractor Using Verilog for High Speed VLSI Architectures " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 7-9, Volume-12,Issue-10

Abstract : This research paper presents a fault-tolerant full subtractor design implemented on an Artix 7 FPGA. To enhance reliability and mitigate the effects of hardware failures, the design incorporates self-checking and self-repairing mechanisms. The full subtractor is designed using Verilog and simulated using Vivado to verify its functionality and fault tolerance. The paper discussed the methodologies employed for fault detection, diagnosis, and correction. The self-checking and selfrepairing techniques were detailed, highlighting their effectiveness in ensuring the circuit's robustness. Experimental results demonstrated the improved reliability and performance of the fault-tolerant full subtractor on the Artix 7 FPGA. Keywords - Fault Tolerance, VLSI, FPGA, Full Subtractor, Self Checking, Self Repairing, Verilog.

Type : Research paper

Published : Volume-12,Issue-10


	\|		PDF	\|	Viewed - 18	\|	Published on 2025-01-24

Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-12,Issue-10

JOURNAL SUPPORTED BY