IJEEDC Performance Analysis of 2-Bitsynchronousup Counter in 45nm CMOS Technology

Journal Paper

Paper Title :Performance Analysis of 2-Bitsynchronousup Counter in 45nm CMOS Technology

Author :Hnin Ngwe Yee Pwint, Tin Tin Hla

Article Citation :Hnin Ngwe Yee Pwint ,Tin Tin Hla , (2023 ) " Performance Analysis of 2-Bitsynchronousup Counter in 45nm CMOS Technology " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 32-37, Volume-11,Issue-10

Abstract : In this paper, a 2-bit synchronous up counter is proposed by using a D flip-flop. It is designed for low power consumption at high speeds. The flip-flops and logic gates used in the 2-bit synchronous up counter circuit are designed with NAND gates only and using Complementary Metal Oxide Semiconductor (CMOS) technology. The parametric analysis is simulated with Cadence Virtuoso software on 45nm technology. A logic diagram for a synchronous counter is presented. Synchronous counters encode the count sequence using logic between the flip-flops and a common clock. The output bits of a synchronous counter change states simultaneously. The performance analysis for a 2-bit synchronous up counter is in terms of power consumption and propagationdelay. Keywords - Synchronous counter, D flip-flop, NAND gate, CMOS technology, Power consumption, Propagation delay.

Type : Research paper

Published : Volume-11,Issue-10


	\|		PDF	\|	Viewed - 35	\|	Published on 2023-12-11

Jan. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	141
Paper Published	:	1771
No. of Authors	:	4924

Published : Volume-11,Issue-10

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