Paper Title :Design and Analysis of CMOS Based D-Type Flip Flop By Using 45nm Technology
Author :May Htet Aung, Tin Tin Hla
Article Citation :May Htet Aung ,Tin Tin Hla ,
(2023 ) " Design and Analysis of CMOS Based D-Type Flip Flop By Using 45nm Technology " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 24-31,
Volume-11,Issue-10
Abstract : Low-power digital systems are the key objective of the field of digital electronics. The usage of very large-scale
integration(VLSI) technologies has been expanding quickly in high-performance computing, wireless communication, and
consumer electronics. Growing leakage power consumption is VLSI technology's greatest challenge. The desire for high
performance and low area implementation of fundamental memory elements arises from the widespread use of memory
storage systems in modern electronics, and D-type flip-flop is a widely recognized state-holding element.In this paper, Dtype
flip-flops with Demorgan's law (DFF-DL) and D-type flip-flops with transmission gates (DFF-TG) have been designed
and analyzed. Small, compact areas are the design goals of the DFF-DL and DFF-TG in order to achieve the lowest
production costs and quicker processing times with a smaller transistor count. Using 45-nm CMOS (complementary metaloxide
semiconductor) technology, their schematics and corresponding layouts have been simulated.In terms of area, power
consumption, and power delay, the performance of these designed circuits is analyzed using the Virtuoso tool of the Cadence
simulation platform.
Keywords - VLSI, D-type flip-flops with Demorgan's law (DFF-DL), D-type flip-flops with transmission gates (DFFTG),
CMOS,Virtuoso
Type : Research paper
Published : Volume-11,Issue-10
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-20200
View Here
Copyright: © Institute of Research and Journals
|
|
| |
|
PDF |
| |
Viewed - 43 |
| |
Published on 2023-12-11 |
|