International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Jan. 2023
Submitted Papers : 80
Accepted Papers : 10
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Acc. Perc : 12%
Issue Published : 120
Paper Published : 1628
No. of Authors : 4469
  Journal Paper


Paper Title :
Comparative Analysis of 32-Bit and 64-Bit Array Multiplier and Modified Booth Multiplier

Author :Rahul Shkaya, Poonam Jindal

Article Citation :Rahul Shkaya ,Poonam Jindal , (2022 ) " Comparative Analysis of 32-Bit and 64-Bit Array Multiplier and Modified Booth Multiplier " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 61-65, Volume-10,Issue-7

Abstract : Abstract - Multipliers are integral part of digital signal processors. Their improved performance is the main factor in the advancement of DSP . This paper presents a comparative analysis of 32-bit and 64-bit array multiplier and modified booth multiplier respectively on basis of various performance parameters in term of power, and area. Implementation of both multipliers have been done in verilog code using xilinx ISE 14.7 software and using FPGA Artix7 family 7a100tcsg324-3 device simulated successfully. Modified booth multipliers have consumed 110 to 400 percent more resources than array multiplier. It also consumes 12 to 250 percent more power than array multiplier for different versions. An exponential rise in resource consumption is observed from 8 to 64-bit version of modified booth multipliers while an exponential jump in power is observed for its 64-bit version. Keywords - Modify booth multiplier, Array multiplier, Modified booth encoder, Partial product reduction.

Type : Research paper

Published : Volume-10,Issue-7


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-18920   View Here

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