Paper Title :Architecture of Femto Cell and its Performance Analysis Under load Testing

Author :S G Srivani, Yashaswini H N, Sumanta Banerjee

Article Citation :S G Srivani ,Yashaswini H N ,Sumanta Banerjee , (2019 ) " Architecture of Femto Cell and its Performance Analysis Under load Testing " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-4, Volume-7,Issue-11

Abstract : This paper describes about a performance analysis based on load testing and the role of power electronics in the femto cells. The evolution of wireless broadband technology avoids the web surfing of the network and improves the data speed and coverage which can be done by using Femtocells without the need of the expensive cell towers. They are low power consumption of 12V for 3G, 6V for 4G ,5V for 5G and low cost user deployed base station able to provide high service in residential, enterprise and metro cells. In order to maintain the stability of the system, the load testing has been done for the long duration by using various tools. If any failure occurs during testing can be analyzed by taking the pcap using wire shark tool. Under real life load condition, the performance of the system can be determined by using the load testing. The role of power electronics in femto technology has been discussed with the importance of PMIC chip. In this proposed paper the architecture of the femto cells along with the load testing and generation of the report for analyzing the performance has been validated. Keywords- Femtocells- Load testing.

Type : Research paper

Published : Volume-7,Issue-11

	|		PDF	|	Viewed - 77	|	Published on 2020-01-06