Paper Title :Bitcell Stability Analysis of SRAM for Submicron Technology

Author :Dharani V T, Jeyalakshmi V

Article Citation :Dharani V T ,Jeyalakshmi V , (2018 ) " Bitcell Stability Analysis of SRAM for Submicron Technology " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 15-18, Volume-6,Issue-8

Abstract : In technology improvement, A system on chip (SoC) is an integrated circuit that integrates all components of a computer or other electronic systems. It may contain digital, analog, mixed-signal, and all on a single substrate. In Digital SoC’s are mostly filled with SRAM (about 55%) and other remaining part will be Graphical Processing Unit (GPU) and Central Processing Unit (CPU). In memory design, different number of MOSFET bit cell targeting the different space requirements and different Process, Voltage and Temperature (PVT) which are affects the SRAM metrics. Static Noise Margin (SNM), Write Margin (WM), Retention Voltage, read current, off current, leakage current variation in the SRAM these are the metrics of the SRAM. This paper analysis lot of research come up with improvement of bitcell, even why 6T transistor are used till today by semiconductor Industry. This paper explains comparison of different number of MOSFET SRAM bitcell with 6T SRAM bitcell. Keywords - SRAM, BTICELL, SoC, PVT, SNM, WM

Type : Research paper

Published : Volume-6,Issue-8

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