International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Nov. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 115
Paper Published : 1589
No. of Authors : 4352
  Journal Paper


Paper Title :
Design & Implementation High Frequency Synchronous 16 X 16 Booth’s Multiplier on Spartan 3E using Customized DCM

Author :Vaibhav.B.Waghmare, A.I.Tamboli

Article Citation :Vaibhav.B.Waghmare ,A.I.Tamboli , (2018 ) " Design & Implementation High Frequency Synchronous 16 X 16 Booth’s Multiplier on Spartan 3E using Customized DCM " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 50-54, Volume-6,Issue-7

Abstract : This paper presents a modified design of Area-Efficient Low power 16x16 Booth’s Multiplier Circuit. In most of the digital circuit, clock is used as a input variable and clock is assigned during stimulation. Xilinx software is used to carry out all the design and implementation process.In this design a a single Digital clock manager(DCM) is used to generated a clock. In booth’s multiplier multiplication to two 16 bit number (multiplier and Multiplicand) is carried out using adders, multiplexer, inverter. Single DCM for high frequency operation. Keywords - Single DCM, Xilinx, Adders, Multiplexers.cadence, utilization Factor.

Type : Research paper

Published : Volume-6,Issue-7


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