IJEEDC Implementation of Effective Integrated on-Chip ESD Protection in Nanoscale CMOS Regime for RFIC

Journal Paper

Paper Title :Implementation of Effective Integrated on-Chip ESD Protection in Nanoscale CMOS Regime for RFIC

Author :P. N. Khairnar, N. K.Khairnar

Article Citation :P. N. Khairnar ,N. K.Khairnar , (2018 ) " Implementation of Effective Integrated on-Chip ESD Protection in Nanoscale CMOS Regime for RFIC " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 39-43, Volume-6,Issue-6

Abstract : Now-a-days scaling of technology has gain lot of importance because of its various advantages. Many digital & analog IC’s are made compact in size using a scaling technology with improved throughput. However with the added advantages there are some disadvantages of this technique, such as leakage current, power dissipation in the form of heat at higher frequencies ESD (Electrostatic Discharge) etc. These disadvantages incorporate the some critical design challenges in RFIC. Among them, in this work we are primarily focus on ESD effect. ESD is happens at higher frequency frequently. It is a main challenge in RFIC design; the survey shows that in all over the world about 70% IC’s were failed due to the ESD event and remaining 30% were because of other factors. We are trying to suggest a methodology to reduce the ESD effect for proper operation of RFIC. The circuitry used for the implementation is on chip integrated technique which differsfrom the conventional technologies. A LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) is used as protectoral architecture. Here LNA (Low Noise Amplifier) is used as an exemplary RFIC core circuit. By using LVTSCR we try to protect it from ESD event.In this research paper we have select operating frequency 5 GHz to 6 GHz. The 130 nm CMOS technology is selected for circuit implementation. LVTSCR is providing good solution for on chip protection of ESD for various digital & analog IC’s. Simulation tool used for design & simulating the design of core circuit (without protection) & RF+ESD circuit (With protection circuit) is Agilent’s Advanced Design System software (ADS). It is very good tool compare to other conventional simulator. After simulation it is observed that there is slightly degrade in gain, noise figure, I/O matching, IIP3 etc. in case of with protection circuit. Keywords - ESD Protection, LVTSCR (Low voltage triggered silicon controlled rectifier), LNA (Low Noise Amplifier), nanoscale etc.

Type : Research paper

Published : Volume-6,Issue-6


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Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-6,Issue-6

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