IJEEDC High-Speed Pipelined 8-Bit RISC Processor Design using Verilog HDL on FPGA

Journal Paper

Paper Title :High-Speed Pipelined 8-Bit RISC Processor Design using Verilog HDL on FPGA

Author :B. Sajidha Thabassum, Triveni, Darshan B.B., Devanabanda Kousik, Diwakar S Mattukumilli

Article Citation :B. Sajidha Thabassum ,Triveni ,Darshan B.B. ,Devanabanda Kousik ,Diwakar S Mattukumilli , (2018 ) " High-Speed Pipelined 8-Bit RISC Processor Design using Verilog HDL on FPGA " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 43-46, Volume-6,Issue-6

Abstract : Because of its capability to extraordinarily quicken a wide variety applications, reconfigurable computing has turned into a subject of a lot of research. Its key component is the capacity to perform calculations in equipment to build execution, while holding a great part of the adaptability of a product arrangement. In this design of 8-bit RISC processor using Harvard architecture, we give a review of the architecture of reconfigurable computing machines, and the software that objectives these machines, code for the modules and underscore on execution improvement pipelining procedure. At long last, we test the speed of the processor by running all kind of instructions. Keywords - Reconfigurable Computing, RISC, Pipeline-Technique, FPGA, Harvard Architecture.

Type : Research paper

Published : Volume-6,Issue-6


	\|		PDF	\|	Viewed - 63	\|	Published on 2018-08-13

Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-6,Issue-6

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