International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Jul. 2024
Submitted Papers : 80
Accepted Papers : 10
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Acc. Perc : 12%
Issue Published : 136
Paper Published : 1737
No. of Authors : 4816
  Journal Paper


Paper Title :
Efficient Routability-Aware Transistor Placement Considering Various Folding Styles for Advanced Technology Nodes

Author :Hong-Yan Su, Yih-Lang Li

Article Citation :Hong-Yan Su ,Yih-Lang Li , (2018 ) " Efficient Routability-Aware Transistor Placement Considering Various Folding Styles for Advanced Technology Nodes " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 23-29, Volume-6,Issue-3

Abstract : Transistor placement is the key step to dominate the quality of standard cell layouts because of the limited routing resource of cell layouts. A routability-aware transistor placement algorithm can then help generate high-quality transistor placements favoring cell routing to reduce potential rule violation and layout quality as well. In this paper we propose aroutability- aware dynamic programming (DP)–based transistor placement algorithm that can efficiently generate transistor placements favoring cell routing and considering diffusion shape constraints. Then, a LEGO-liked assembling method considers the issue of different folding styles to generate transistor placements of high-driving cells. Our results show that the proposed methods can have dramatic routability and runtime improvement compared to existing works. Indexterms - Standard cell, Transistor placement, Dynamic programming (DP), LEGO.

Type : Research paper

Published : Volume-6,Issue-3


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