A Comparison of Hard and Soft Viterbi Decoder with High Speed Low Power Consumption for TCM Decoders
The main objective of this project is to design a low-power, low-latency and high speed Viterbi Decoder for high
rate convolutional codes. It is well known that in the overall power consumption of Trellis-Coded Modulation (TCM)
decoders Viterbi Decoder (VD) is the dominant module determining. Using the pre-computation architecture incorporated
with T-algorithm for Add Compare Select Unit (ACSU) and with the State Exchange (SE) algorithm for the Survivor Memory
Unit (SMU) design, which can effectively reduce the power Consumption and increase the decoding speed. Viterbi decoder
is a common module in communication system in which power and decoding latency are constraint. Register exchange (RE)
architecture has the lowest decoding latency. However, it is not suitable for communication system because of its high power
consumption. In this project, we propose a new SMU architecture which combines the concept of the trace-forward and
trace-back. Besides, we present a power efficient architecture for the proposed SMU algorithm. Viterbi decoder is a common
module in communication system, which has the requirement of low power and low decoding latency. The conventional
register exchange (RE) algorithm and memory-based trace-back (TB) algorithm cannot meet both constraints of power and
decoding latency. In this project, we propose a new Survivor Memory Unit (SMU) algorithm, named State Exchange (SE)
algorithm. The SE algorithm uses the trace- forward unit (TFU) to run the decoding operation for low decoding latency.
Index Terms - Lattice Encoding/Decoding, Convolutional Lattices, BCJR Lattice Decoder, Construction A/D,
modulo-Lattice Additive Noise.