Device Modeling Solutions To Reduce Gidl Current In Low Power VLSI Circuits
Leakage current reduction is of primary importance as the technology scaling trends continue towardsdeep submicrometer regime. One of the leakage mechanisms which contribute significantly to power dissipation is the Gate Induced
Drain Leakage (GIDL). GIDL sets an upper limit on the VLSI MOSFET scaling and may even lead to device breakdown.
Thus, in order to improve performance, static power consumption becomes a major concern in such miniaturized devices.
With the CMOS technology in the nanometer regime, metal gates emerge as a powerful booster over the poly-Si gates,
keeping the leakage mechanisms in control. This work presents a systematic study of the Gate Induced Drain Leakage
current reduction by changing the gate workfunction. In this work, an attempt has been made to model the metal gates in the
field equations in the gate-drain overlap region. The modeling has been accomplished by taking the physical property of the
metals into account i.e. the workfunction. The analytical model has been used to study the impact of gate workfunction
engineering on GIDL. The model includes the calculation of band bending, the resultant electric field in the gate-drain
overlap region and the GIDL current. It has been observed that the electric field and the GIDL current decreases as the gate
workfunction is increased continuously from 4.0~5.2 eV. Further, the results are more interesting at low applied voltages
where the decrease in the current is of about 6 orders of magnitude as compared to that at higher voltages.