Paper Title
2-Dimensional Analysis of the Partial SOI Type Isolation MOSFET with Different Buried Insulator Dielectric

As scaling down the DRAM cell size, the conventional MOSFET degrade device performance in terms of short channel effects. A solution for these issues is the Silicon-on-Insulator (SOI) MOSFET. However, it suffers from low threshold voltage, back gate interface issue, floating body effect such as kink effect, and high price, even though it shows low power consumption, self-limited shallow junction, improved Drain Induced Barrier Lowering (DIBL). To overcome the problem, a new device partial SOI type isolation MOSFET has been introduced [1]. The structure of this device is obtained by penetrating the insulator below the N type doped region near the drain region. And the lateral encroachment length of the buried insulator is controlled by isotropic etch time. This device can effectively improve short channel effects while improving the disadvantages of the conventional MOSFET and the SOI MOSFET. In the paper, the partial SOI type isolation MOSFET having 100nm node of gate channel length is investigated using Sentaurus TCAD 2-D device simulator [2]. And This study was conducted to investigate the performance of partial SOI type isolation MOSFETs according to the dielectric constant. The results show that the low-k dielectric of the buried insulator increases the threshold voltage and improves the DIBL characteristic due to decrease in the depletion region width near the drain region. Also, it is confirmed that the kink effect disappears unlike the SOI MOSFET due to the difference in structure. Index Terms - Drain Induced Barrier Lowering (DIBL), Silicon-On -Insulator (SOI), Short Channel Effect (SCE)