Paper Title
Reusable And Reconfigurable Approach To Functional Verification Of A Chip

Abstract
Verification is a process used to demonstrate the functional correctness of a design. Also called logic verification or simulation. This paper demonstrates the functional verification planning process for creating a reusing and reconfigurable verification systems (test bench) which can be used to verify different versions of a component design with minimum changes in the verification environment by using minimum components for creating verification environment.