Paper Title :A Survey on Power Optimization of 8-Bit Magnitude Comparator using Pre-Computation and Binary Decision Diagram

Author :Bindu R, M C Chandrashekhar, M Z Kurian

Article Citation :Bindu R ,M C Chandrashekhar ,M Z Kurian , (2017 ) " A Survey on Power Optimization of 8-Bit Magnitude Comparator using Pre-Computation and Binary Decision Diagram " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 22-24, Volume-5,Issue-9

Abstract : Power optimization is the primary constraint in recent technologies.Due to transistor scaling,clock frequency and chip transistor count,power dissipation increases.The need of low power design is a major concern in high performance digital systems.This can be achieved by using Binary Decision Diagram (BDD) and pre-computation logic.Symbolic model checking is used in verification of many hardware circuits.This is mainly done by BDD representation which gives the stable performance.The area and power consumption in the BDD is determined by the total number of nodes present in it.Precomputation is a powerful sequential logic optimization technique which is selectively precomputing the output logic values of the circuit one clock cycle earlier than they required.These precomputed values is used to minimize internal switching activity in the next clock cycle.These two techniques is used in designing the 8-bit magnitude comparator specially for low power gives the better performance and in reduction in area and time delay. Keywords - BDD, Precomputation, Perfomance.

Type : Research paper

Published : Volume-5,Issue-9

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