International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Sep. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 91
Paper Published : 1444
No. of Authors : 3905
  Journal Paper

Paper Title
Micro-Archetecture Design of Risc V Microprocessor using VHDL

The freedom of compatibility with old designs and the use of microprocessor technology led to a renaissance in computer design which emphasized both architectural innovation and efficient use of technology improvements. The paper proposes a micro-architecture design of a 32 bit RISC V microprocessor, the proposed micro-architecture is meritorious compared to the earlier versions since the RISC-V processor ISA keeps the source (rs1 and rs2) and destination (rd) registers at the same position in all formats to simplify decoding, also immediates are packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity. In particular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry. The prominent features which make RISC V better than other ISAs are RISC-V ISA is very easy to decode and all instructions in it are easy to schedule and do hazard checking. Optimization is done by pipelining the design in order to improve the processor Clock cycle Per Instruction, however most of the time there are data dependencies which will increase the CPI. In order to improve the CPI, a data forwarding unit is incorporated in the execution stage to solve the same. The Instruction set architecture used for the design is the RISC - V (Version – 2.0000) from the University of Berkeley (UCB). The entire project phase comprises micro-architecture design of RISC – V ISA (Integer computational and control transfer instructions) processor and the elimination of the structural hazard and the data hazards. Elimination of the structural hazard is done by designing a separate memory for the instructions and data. Data hazards are eliminated by the design of the forwarding unit which overcomes the problem of data dependencies. Keywords: CPI, ISA, RISC V

Author - Vinay Reddy Narayana

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