International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
current issue
Volume-8,Issue-3  ( Mar, 2020 )
  1. Volume-8,Issue-2  ( Feb, 2020 )
  2. Volume-8,Issue-1  ( Jan, 2020 )
  3. Volume-7,Issue-12  ( Dec, 2019 )

Statistics report
Jun. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 87
Paper Published : 1413
No. of Authors : 3823
  Journal Paper

Paper Title
Generation of on-Chip Functional Tests With Reduced Delay and Power

This paper describes an on-chip test generation method for functional broadside tests.The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states.Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR.The on-chip generation of functional broadside tests require simple hardware and achieved high transition fault coverage for testable circuits.Further,power and delay can be reduced by using Bit Swapping LFSR(BS-LFSR).This technique yields less number of transitions for all pattern generation.Bit-swapping(BS) technique is less complex and more reliable to hardware miscommunications. Index Terms— Built-in test generation, functional broadside tests, reachable states, Bit Swapping LFSR(BS-LFSR).

Author - Hemanth Kumar Motamarri, B Leela Kumari

| PDF |
Viewed - 63
| Published on 2017-01-04
IRAJ Other Journals
IJEEDC updates
Volume-8,Issue-1(Jan,2020) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740