International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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May. 2022
Submitted Papers : 80
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  Journal Paper


Paper Title :
The FPGA Implementation of Viterbi Algorithm in Grand Alliance ATSC Systems

Author :S.S. Deshpande, D.L.Gadhe.

Article Citation :S.S. Deshpande ,D.L.Gadhe. , (2016 ) " The FPGA Implementation of Viterbi Algorithm in Grand Alliance ATSC Systems " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 49-52, Volume-4,Issue-11

Abstract : It is well known that data transmission over wireless channel are affected by attenuation, distortion, interference and noise which affect receiver abilities to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. They play important role in Digital communications, especially when channel is noisy and introduces errors in transmission channel. Today data reconstruction in digital communication system requires design of highest throughput rate. Convolutional codes are used in many communication system due to excellent error control performance .Convolutional coding is done by combining fixed number of input bits .The input bits are stored in fixed length shift registers, they are combined with help of mod-2 adders. Operation is similar to binary convolution, and hence known as convolutional coding .The parallel process Viterbi Decoder with pipelining uses 3-bit soft decision decoding for estimation of original data streams. Power consumption is reduced, moreover speed of processing is increased.[5] Keywords- Convolution encoders, Viterbi Decoders, ATSC system.

Type : Research paper

Published : Volume-4,Issue-11


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