Paper Title :Synthesis of Triple DES 64 bits Processor using VLSI

Author :Gurtek Singh, Gurdit Saggu

Article Citation :Gurtek Singh ,Gurdit Saggu , (2022 ) " Synthesis of Triple DES 64 bits Processor using VLSI " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 5-9, Volume-10,Issue-10

Abstract : Abstract - The protection of data and authenticity are very important role in many applications in electronics system. Data security is used in our daily life such as electronic fund transfer, banking ATM; business insurance etc. Our design implement on a Vertex xcv5vlx30-3ff324 device. To improve the performance, we use single DES three times with different key for encryption and decryption. In this design we present an efficient implementation design of triple data encryption standard using VHDL technology. Implementation of single DES and TDES are tested successfully using VHDL technology. In our project when we compare the parameters like numbers of slices utilization (area), frequency and throughput of all the TDES or DES. So where these parameters are important criterion there we should prefer small design to implement. Keywords - DES, Encryption, Decryption, Cryptography, Simulation, Synthesis, TDES, Cipher.

Type : Research paper

Published : Volume-10,Issue-10

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