IJEEDC An Area Efficient Design of MIDORI-64 for IOT Applications

Journal Paper

Paper Title :An Area Efficient Design of MIDORI-64 for IOT Applications

Author :Aakanksha Baghel, Zeesha Mishra, Onika Parmar, Amit Singh Rajput

Article Citation :Aakanksha Baghel ,Zeesha Mishra ,Onika Parmar ,Amit Singh Rajput , (2022 ) " An Area Efficient Design of MIDORI-64 for IOT Applications " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 97-102, Volume-10,Issue-7

Abstract : Abstract - Modern cryptographic algorithms are the backbone of data security and privacy for highly confidential and classified information. The Internet of Things (IoT) is a system of interconnected devices which share data and information in real time. The growing number of linked devices in IoT applications has raised serious security problems. Lightweight cryptographic algorithms seem to be the solution for the challenge of providing security solutions to resource-constrained devices. Midori is one such algorithm which follows SPN structure. Midori is available in two block sizes namely 64-bit and 128-bit, both uses 128-bit key size. The proposed designs are implemented in verilog HDL using Xilinx ISE Design suite. Comparison with different families of FPGA has been done. There is a improvement of 20.33% in area (slices), and 50.29% in throughput. Keywords - Cryptography, LWC, Midori, FPGA, Slices, Throughput

Type : Research paper

Published : Volume-10,Issue-7


	\|		PDF	\|	Viewed - 39	\|	Published on 2022-11-17

Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-10,Issue-7

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