IJEEDC Independent Gate TFETS for Logic Realization: A Review

Journal Paper

Paper Title :Independent Gate TFETS for Logic Realization: A Review

Author :Sourav Kumar Biswal

Article Citation :Sourav Kumar Biswal , (2022 ) " Independent Gate TFETS for Logic Realization: A Review " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 72-75, Volume-10,Issue-7

Abstract : Abstract - Independent gate tunnel FETS have the potential to replace Cmos logic which can have less area by reducing number of transistor required to implement a logic and can operate on low voltages. Independent gate devices with strong coupling between back and front gates can generate different logic by using different device threshold voltages, which can reduce the number of transistors used in circuits. In this article we have discussed the various device structure and techniques available to optimizetheindependentgateTFETtoachievefunctionalitysimilartoaCmosAND,ORlogicgate. Keywords - IG TFET, Ambipolar Current, Logic Realization in TFETs

Type : Research paper

Published : Volume-10,Issue-7


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Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-10,Issue-7

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