IJEEDC Design and Implementation of 64 X 64 Bit Vedic Multiplier

Journal Paper

Paper Title :Design and Implementation of 64 X 64 Bit Vedic Multiplier

Author :Vijendra Bairwa, Poonam Jindal

Article Citation :Vijendra Bairwa ,Poonam Jindal , (2022 ) " Design and Implementation of 64 X 64 Bit Vedic Multiplier " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 66-71, Volume-10,Issue-7

Abstract : Abstract - Multipliers play an important role in digital signal processing (DSP) applications. It improves the speed and reduces resource consumption while designing FIR filters. Vedic mathematics provides many formulas for fast multiplications. Urdhva – tiryagbhyam is one such formula for fast multiplication. It can be used to design fast multipliers. This paper presents a new 64-bit multiplier based on this formula.The multiplier has been implemented using Xilinx ISE 14.7 software. The implementation has been carried out on four FPGA families: Kintex-7, Virtex-6, Virtex-5, and Spartan-6, and a comparative analysis has been with the existing design in the terms of area and timing delay. An improvement of 14.89% is reported using Virtex-6 FPGA. While an 8.29% reduction in resource consumption is achieved on Spartan-6 implementation compared to the existing design. Keywords - Urdhva – tiryagbhyam sutra, 2x2 bit Vedic multiplier,4x4 Vedic multiplier.

Type : Research paper

Published : Volume-10,Issue-7


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Mar. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	143
Paper Published	:	1781
No. of Authors	:	4956

Published : Volume-10,Issue-7

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