International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Sep. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 114
Paper Published : 1570
No. of Authors : 4287
  Journal Paper


Paper Title :
Comparative Performance Analysis of Novel Comparator Architectures

Author :Siddhant Ahlawat, Siddharth, Saransh Sehgal, Akshay Mann

Article Citation :Siddhant Ahlawat ,Siddharth ,Saransh Sehgal ,Akshay Mann , (2022 ) " Comparative Performance Analysis of Novel Comparator Architectures " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 21-26, Volume-10,Issue-5

Abstract : Abstract - Comparators are a key component of most analog to digital converters and many other vlsi circuits. The performance of the comparator is crucial in determining the overall speed of the analog to digital converter. Therefore architecture, stability and performance of the comparator is of utmost importance and needs to be analyzed and evaluated. Power consumption of the comparator plays a huge role in determining the efficiency of the comparator. Delay caused by the comparator is another paramount component for determining the performance and quality of the comparator architecture. Practical aspects like variation in performance of the comparator due to external factors like temperature changes in the environment also need to be studied for ensuring reliability of comparator performance for real world applications. In this paper five different comparator architectures are designed on 180nm technology nodes to analyze and compare their performance parameters such as power/energy consumption and Delay produced. The variation in power consumption with changing temperature is also evaluated for each comparator. Keywords - Area-efficient, Low power, CSLA, Binary To Excess One Converter, Multiplexer

Type : Research paper

Published : Volume-10,Issue-5


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