International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
current issue
Volume-8,Issue-7  ( Jul, 2020 )
  1. Volume-8,Issue-6  ( Jun, 2020 )
  2. Volume-8,Issue-5  ( May, 2020 )
  3. Volume-8,Issue-4  ( Apr, 2020 )

Statistics report
Sep. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 91
Paper Published : 1444
No. of Authors : 3905
  Journal Paper

Paper Title
Performance Measurement Of Digital Modulation Scheme Using Simulink And System Generator Blockset For FPGA

This paper gives the technique for the performance measurement of digital modulation schemes since the digital modulation schemes are superior as compared to analogue modulation schemes. The performance characteristics like bit error rate(BER), SNR, SNDR can be used to evaluate the performance of digital modulation techniques. The system will be able to measure the performance of more than one modulation scheme. This paper presents the results using MATLAB Simulink, the proposed system will be implemented using FPGA. Keyword—Bit Error Rate (BER), Signal to noise ratio (SNR), Signal to noise and distortion ratio (SNDR), FPGA.

Author - Monika choudhari S. R. Patil

| PDF |
Viewed - 87
| Published on 2015-04-04
IRAJ Other Journals
IJEEDC updates
Volume-8,Issue-1(Jan,2020) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740