International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Jul. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 136
Paper Published : 1737
No. of Authors : 4816
  Journal Paper


Paper Title :
An Efficient and Reliable Architecture for Fault Tolerant Adder Design

Author :Fızza Mehfooz, Muhammad Iram Baıg

Article Citation :Fızza Mehfooz ,Muhammad Iram Baıg , (2021 ) " An Efficient and Reliable Architecture for Fault Tolerant Adder Design " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 13-16, Volume-9,Issue-12

Abstract : Abstract - The high-speed error resilient adders are of great importance in digital system design and signal processing. Carry Select Adder (CSeA) is the most frequently implemented fast adder in digital systems to improve system speed. The principal purpose of this research work is to propose a method that can detect and tolerate faults in adders, thereby reducing area overhead. The goals of this research include a) Formulating a specific fault model for adders b) Technique to detect and localize the faults in the adders c) Design of a fault resilient adder by avoiding the detected faults. This work is mainly emphasizing on designing a fault tolerant carry select adder using hardware redundancy configurations for better reliability. The proposed technique reduces hardware complexity significantly, and delays to make an efficient and reliable fault tolerant adder design. This design utilizes pass transistor logic (PTL) instead of CMOS transistor logic. The PTL design utilizes fewer transistors, which helps to reduce area overhead significantly and is more efficient, as the percentage overhead is -11.27% and the transistor count is only 252 for the 4-bit adder size. Keywords - Fault Tolerant, CSeA, Overhead, Self-Checking, Efficient, Transistor

Type : Research paper

Published : Volume-9,Issue-12


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