International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 89
Paper Published : 1423
No. of Authors : 3841
  Journal Paper

Paper Title
Design Of Dual Edge Triggered Sense Amplifier Flip-Flop For Low Power Application

Abstract
Dual edge triggered sense amplifier flip-flop for low power application is presented in this paper. This system is implemented using advanced Electronic Design Automation (EDA) tools. Now a day as Complexity means transistor on chip increases the power requirement also get increases, so the power is an important in VLSI design. In VLSI circuit the major design issues are power consumption and speed. Power dissipation can be reducing by a compromise of variety of components. Power consumption is also data dependent in VLSI circuit (like in multipliers). This paper gives modular approach for optimizing power consumption. Low power design is not only used in small size devices but also in high performance computational devices. Flip-flop is important element to determine the power consumption in VLSI design level. In this paper dual edge triggered flip-flop’s power consumption and optimization of delay is primarily figure of merit. To reduce power consumption, we have used explicit pulse generator and latch using precharching transistor in static output –controlled discharge flip-flop (SCDFF) and the conditional discharge technique is inserted. The dual-edge triggered static pulsed flip-flop (DSPFF) removes unnecessary transitions. Adaptive clocking dual-edge triggered sense amplifier flip-flop (ACSAFF) removes the redundant transition of internal nodes. Keywords- Small Delay; Low-Power; Dual-Edge Triggered Flip-Flop; Static Output –Controlled Discharge Flip-Flop; Adaptive Clocking Dual-Edge Triggered Sense Amplifier Flip-Flop; Sense Amplifier


Author - Kishori S. Ghukse, N. A. Pande, Minal S. Ghute

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