International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Statistics report
Jan. 2021
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 93
Paper Published : 1465
No. of Authors : 3971
  Journal Paper

Paper Title
Design and simulation of Vernier Ring Oscillator TDC with Improved Resolution

TDC plays a very important role in most of the in high energy nuclear physics time of flight experiment for achieves high resolution. The traditional time interval experiment measurement totally depend on such kind of methods like Time-to-Amplitude Conversion, Vernier method, Delay Locked Loops (DLL), Tapped Delay Lines (TDL), Differential Delay Lines (DDL), current -Integration TDC, & Counter-Based TDC etc. Many time-of-flight (TOF) applications required measurement of the time intervals between two events. Time to digital converter is becoming more suitable for these kinds of applications because it measures the time difference between two pulses and gives time difference as a digital output code. However, basic TDC needs much higher clock frequency to measure smaller time intervals between two events in terms of picoseconds. The main advantage of migrating TDC in the FPGA paradigm is making the best of its configuration and reconfiguration capabilities. The resolution below the minimum gate delay is achieved by employing Vernier oscillator technique. We present here a high resolution TDC based on vernier ring oscillator principle of nearly 70ps resolution. Keywords - TOF, Time to Digital Converter, Vernier Delay Line, Field Programmable Gate Array, Ring Oscillator.

Author - Pooja Gupta, Pooja Saxena

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| Published on 2019-12-19
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