International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Mar. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 85
Paper Published : 1402
No. of Authors : 3795
  Journal Paper

Paper Title
Design and Implementation of Low Power High Speed 4*4 bit Multiplier using Vedic Mathematics

Abstract
Multiplier plays an significant role in electronic circuits. In many apps, such as digital signal handling, microprocessors and micro commuters, these are the primary blocks. In this document we propose a high-speed Vedic multiplier pipeline, which contains Vedic mathematics as an old method with a distinctive method and a distinct sutra. This article discusses Sutra Urdhva Triyagbhyam (UT), which is effective in terms of the multiplier's field and velocity. We have introduced distinct architectures to increase the velocity of the multiplier, where the complete addition from distinct logics is used. The Vedic multiplier in this document is intended with a modified full-adder that uses less slices and delay is reduced. The model is simulated using Xilinx 14.7 version and synthesized using RTL compiler. Keyword - Vedic Multiplier, Full Adder using Multiplexer, Ripple Carry Adder.


Author - Sumit Kumar, Pooja Saxena

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| Published on 2019-12-19
   
   
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