International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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May. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 110
Paper Published : 1545
No. of Authors : 4201
  Journal Paper


Paper Title :
BIST Architecture for Combinational Circuit

Author :Vanya Gupta, Garima Singh, Abhijit Asati

Article Citation :Vanya Gupta ,Garima Singh ,Abhijit Asati , (2019 ) " BIST Architecture for Combinational Circuit " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-8, Volume-7,Issue-5

Abstract : Design for testability adds an additional feature to an integrated circuits (IC), which simplify the manufacturing tests to detect faults in a hardware. In this paper we present testability analysis through a built-in-self-test (BIST). This scheme targets stuck-at-fault by applying test vectors to circuit under test (CUT) through test pattern generator (TPG) and recording the response using output response compactor (ORC) where the operation of different blocks of BIST is coordinated by BIST controller. The BIST circuit comprise of hold logic and a signature generation element. The modeling of the BIST for combinational logic circuit is performed using Verilog and its implementation is done using RTL compiler. A BIST for combinational CUT is carried out using three types of response analyzers namely Serial Input Signature Register (SISR), Serial Signature Analyzer (SSA) and Parallel Signature Analyzer (PSA), which are synthesized utilizing 90 nm TSMC technology library. These designs are synthesized using RTL compiler to generate area, power and timing results for each case. Keywords - BIST, CUT, LFSR, SISR, SSA, MISR, DFT

Type : Research paper

Published : Volume-7,Issue-5


DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-15458   View Here

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