International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Volume-7,Issue-12  ( Dec, 2019 )
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Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
BIST Architecture for Combinational Circuit

Abstract
Design for testability adds an additional feature to an integrated circuits (IC), which simplify the manufacturing tests to detect faults in a hardware. In this paper we present testability analysis through a built-in-self-test (BIST). This scheme targets stuck-at-fault by applying test vectors to circuit under test (CUT) through test pattern generator (TPG) and recording the response using output response compactor (ORC) where the operation of different blocks of BIST is coordinated by BIST controller. The BIST circuit comprise of hold logic and a signature generation element. The modeling of the BIST for combinational logic circuit is performed using Verilog and its implementation is done using RTL compiler. A BIST for combinational CUT is carried out using three types of response analyzers namely Serial Input Signature Register (SISR), Serial Signature Analyzer (SSA) and Parallel Signature Analyzer (PSA), which are synthesized utilizing 90 nm TSMC technology library. These designs are synthesized using RTL compiler to generate area, power and timing results for each case. Keywords - BIST, CUT, LFSR, SISR, SSA, MISR, DFT


Author - Vanya Gupta, Garima Singh, Abhijit Asati

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