IJEEDC Low Power FGMOS Current-Mode Multiplier Circuits With Applications In Analog Signal Processing

Journal Paper

Paper Title :Low Power FGMOS Current-Mode Multiplier Circuits With Applications In Analog Signal Processing

Author :Abirami N, Vijayalakshmi M, Viji K, J Shafiq Mansoor

Article Citation :Abirami N ,Vijayalakshmi M ,Viji K ,J Shafiq Mansoor , (2014 ) " Low Power FGMOS Current-Mode Multiplier Circuits With Applications In Analog Signal Processing " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 23-26, Volume-2,Issue-12

Abstract : The current mode analog multiplier circuit using floating gate MOS (FGMOS) transistors operating in saturation region is presented. Since FGMOS stores charge for long period of time, the presented structure have the advantage of low supply voltage and low power consumption. The squaring characteristics of MOS transistor improve frequency response and the bandwidth of a multiplier. The proposed structure is designed for implementing in 180-nm CMOS technology in cadence virtuoso environment. The circuit’s power consumption and supply voltage is about 47.26 µw and 1v respectively. Keywords- Current-Mode Operation, Floating Gate Mos, Multiplier, Translinear Loop.

Type : Research paper

Published : Volume-2,Issue-12


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Jan. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	141
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No. of Authors	:	4924

Published : Volume-2,Issue-12

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