International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
.
current issue
Volume-8,Issue-8  ( Aug, 2020 )
ARCHIVES
  1. Volume-8,Issue-7  ( Jul, 2020 )
  2. Volume-8,Issue-6  ( Jun, 2020 )
  3. Volume-8,Issue-5  ( May, 2020 )

Statistics report
Oct. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 92
Paper Published : 1453
No. of Authors : 3932
  Journal Paper

Paper Title
Serial One-Step Majority Logic Decoder For EG-LDPC Code

Abstract
In the modern digital system design the reliability and security of memories are essential considerations. As technology scales, memory devices become larger and more powerful error correction codes are needed to protect memories from soft errors. Low Density Parity Check (LDPC) Codes are the class of linear block codes which provide near capacity performance on large collection of data transmission channels while simultaneously feasible for implementable decoders. One specific type of LDPC codes, namely EG- LDPC are used due to their fault secure detection capability, higher reliability and lower area overhead. One of the existing methods for error detection in EG-LDPC is the one step Majority Logic Decoder (MLD) method used to detect the error in memory device itself.


Author - M.Pramodh Kumar, S.Murali Mohan

| PDF |
Viewed - 76
| Published on 2014-11-07
   
   
IRAJ Other Journals
IJEEDC updates
Volume-8,Issue-1(Jan,2020) Want to join us ? CLick here http://ijeedc.iraj.in/join_editorial_board.php
The Conference World

JOURNAL SUPPORTED BY

ADDRESS

Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740