International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
.
current issue
Volume-8,Issue-7  ( Jul, 2020 )
ARCHIVES
  1. Volume-8,Issue-6  ( Jun, 2020 )
  2. Volume-8,Issue-5  ( May, 2020 )
  3. Volume-8,Issue-4  ( Apr, 2020 )

Statistics report
Sep. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 91
Paper Published : 1444
No. of Authors : 3905
  Journal Paper

Paper Title
Design an Efficient Majority Logic GDI Carry- Select Adder

Abstract
In modern VLSI, CMOS technologies are invented and the size is reducing day by day. So the complexities increases resulting into the high integration. Here a 1 bit and 8 bit Carry Select Adder (CSLA) is proposed to obtain efficient design. By introducing traditional full adder, conventional CSLAs are designed. The complexity obtained in the system is represented from power consumption and area. So this problem is solved by implementing modern technique on the CSLA. Moreover the logic gates are designed which is based on the technique of Gate Diffusion Input (GDI). It can observe that the both area and power consumption is reduced from proposed design. It is shows that the power for 1-bit is reduced and the power for 8-bit is reduced. The simulation results exhibits that the GDI design performs better than the CMOS logic design. Index terms - CSLA(Carry Select Adder (CSLA); GDI (Gate Diffusion Input) Technique; RCA (Ripple Carry Adder).


Author - N. Gopi Chand, S. Baba Fariddin, Sk. Mohiddin

| PDF |
Viewed - 52
| Published on 2018-12-29
   
   
IRAJ Other Journals
IJEEDC updates
Volume-8,Issue-1(Jan,2020) Want to join us ? CLick here http://ijeedc.iraj.in/join_editorial_board.php
The Conference World

JOURNAL SUPPORTED BY

ADDRESS

Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740