International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
current issue
Volume-7,Issue-12  ( Dec, 2019 )
  1. Volume-7,Issue-11  ( Nov, 2019 )
  2. Volume-7,Issue-10  ( Oct, 2019 )
  3. Volume-7,Issue-9  ( Sep, 2019 )

Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
A Novel Design of Bit-Slice Matrix Multiplier for RSFQ using Shadow Latch

In this paper, we demonstrated a high speed energy efficient approximate multiplier. We contemplate an approach which is to round the operands to nearest exponent to two. The proposed system is applied for both unsigned and signed multiplications. A 4-bit bit-slice matrix multiplier is exploited for 32-bit rapid multiple-flux-quantum (RMFQ) artificial intelligence processor is proposed in this paper. The multiplier mainly includes bit-slice multipliers which is 4-bit and 4-bit bit-slice adders. The unsigned integer matrixes multiplication is contrivance by control signals. The result shows that our method simplifies the circuit complexity, truncates the hardware costs and allows extending the matrix multiplier to a smaller or larger number of bits. Keywords - Accuracy, approximate computing, energy efficient, error analysis, high speed, multiplier.

Author - T. Prasad Babu, A. Siva Prasad, T. Indira

| PDF |
Viewed - 45
| Published on 2018-12-29
IRAJ Other Journals
IJEEDC updates
Volume-7,Issue-12(Dec,2019) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740