International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Volume-7,Issue-12  ( Dec, 2019 )
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Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
Memory Based Floating Point FFT Processor using Memory Block Vector

A hypothesized conflict-free address scheme which is efficient for arbitrary point memory-based fast Fourier transform (FFT) processor was exhibited in this paper. In the proposed scheme, a high radix decomposition method was utilized for reducing the levels of computation and small radix connected multipath-delay-commutator butterfly units were adopted to eliminate the complexity of the computation engine as well. Several important functions of memory-based FFT processor were combined together, including the continuous-flow mode, variable computation size and conflict-free address scheme. Moreover, a prime factor algorithm was employed to decrease the multiplications and the twiddle factor storage when there subsist prime factors in the decomposition. At last, a unified Winograd Fourier transform algorithm (WFTA) butterfly core was designed for the small 2, 3, 4, 5 point DFTs to reduce the computation complexity further. Keywords - Conflict-free address scheme, long-term evolution (LTE), memory-based fast Fourier transform (FFT) processor, prime factor algorithm (PFA), Winograd algorithm.

Author - S. Butchi Babu, T. Naga Mounika, Hemasri Chundi

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| Published on 2018-12-29
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