International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Volume-7,Issue-12  ( Dec, 2019 )
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Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
Fault Tolerance Improvement of The Secured Circuits

Abstract
One of the major problems in testing a system-on-chip is dealing with the optimal choice of the test sequence. In this paper, we propose an efficient test sequence for TMR secure circuits. The test sequence is a high level method based on three pulsations. An extension to the sequence with one pulsation is proposed and by simulation results its effectiveness in achieving a higher fault tolerance interval is demonstrated.


Author - Ghania Ait Abdelmalek, Rezki Ziani, Rabah Mokdad

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| Published on 2018-12-11
   
   
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