Paper Title :Area–Delay–Power Efficient Carry-Select Adder

Author :Sareeka Tulshiram Deore

Article Citation :Sareeka Tulshiram Deore , (2018 ) " Area–Delay–Power Efficient Carry-Select Adder " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 46-49, Volume-6,Issue-9

Abstract : In this paper, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)- based and CSLA using common Boolean logic CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have observe all the logic operation’s and eliminated all the redundant logic operations those performs a repeated operations like carry generation present in the conventional CSLA and proposed a new logic formulation with minimum operations for CSLA. In the proposed CSLA, the carry is generating before final sum generation by using carry select (CS), which is different from the conventional approach. So that delay has been reduced. CS and generation units’ logic operations are performed by using bit patterns of two anticipating carry words and fixed cin bits. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 18% less area than the BEC-based SQRT-CSLA for 32 bit CSLA , which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. Keywords - CSLA, BEC, CS, SQRT, ADP.

Type : Research paper

Published : Volume-6,Issue-9

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