Paper Title :Design of n-bit Tree based Comparator
Author :Mahalakshmi K S, Jayashree H V
Article Citation :Mahalakshmi K S ,Jayashree H V ,
(2018 ) " Design of n-bit Tree based Comparator " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 53-55,
Volume-6,Issue-8
Abstract : Reversible logic gates gain attention in recent years due to its low power consumption ability. It is used in
advance computing, DNA computing, quantum computation, low power CMOS design and nanotechnology. In this paper an
n-bit optimized tree based reversible comparator is proposed using existing reversible logic gates. The design is realized and
the parameters garbage output, Ancilla/constant input, quantum cost and delay are calculated. The design is simulated using
ISE simulator (Xilinx 14.7, spartan 6).
Keyword - Reversible Gate, Quantum Cost, Ancilla Input, Garbage Output, Comparator.
Type : Research paper
Published : Volume-6,Issue-8
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-13349
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Copyright: © Institute of Research and Journals
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Published on 2018-10-29 |
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