IJEEDC 4 Bit Vedic Multiplication using Threshold Logic Memristive CMOS Technology

Journal Paper

Paper Title :4 Bit Vedic Multiplication using Threshold Logic Memristive CMOS Technology

Author :Merlyn Mariyam Varghese, Lijesh L, Shahzad A. S

Article Citation :Merlyn Mariyam Varghese ,Lijesh L ,Shahzad A. S , (2018 ) " 4 Bit Vedic Multiplication using Threshold Logic Memristive CMOS Technology " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 42-46, Volume-6,Issue-8

Abstract : The fourth circuit element is memristors, that are mostly used in brain-like circuits and also in computing systems. Brain-like circuits has an advantage of fault tolerance and generalization ability of logic gates. The major problem that arises in the progress of implementing brainlike circuits in VLSI is the scalability of networks and limitation of solving large Boolean functions. In this paper, a 4 bit Vedic multiplier using memristor threshold logic circuit was designed. The proposed memristive cmos circuit is a combination of memristive circuits and cmos circuit, which provide the lower chip area, lower total harmonic distortion, and controllable leakage power. For the designing and simulation of the proposed system Ltspice IV tool was used. Keywords - Area-efficient, Low power, CSLA, Binary to excess one converter, Multiplexer.

Type : Research paper

Published : Volume-6,Issue-8


	\|		PDF	\|	Viewed - 68	\|	Published on 2018-10-29

Jan. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	141
Paper Published	:	1771
No. of Authors	:	4924

Published : Volume-6,Issue-8

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