International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
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Statistics report
Sep. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 91
Paper Published : 1444
No. of Authors : 3905
  Journal Paper

Paper Title
Design and Implementation of Synchronous 4-Bit up Counter using SSASPL

This paper represent design of synchronous 4-bit Up counter utilizing SSASPL. The SSASPL is executed utilizing 7 transistors. A fast and area effective synchronous Up counter is required in numerous applications viz. computerized recollections, ADCs, DACs, micro-controller circuits, recurrence dividers, recurrence synthesizer and so forth. Lower region and fast may met by decreasing size of equipment. Henceforth as the applications are expanding, interest for smaller size and longer life batteries increments. It normally comprises of a memory component, which is utilizing flip-flops and a combinational component, which is generally executed utilizing logic gates. Logic gates are logic circuits with at least one info terminals and one yield terminal in which the yield is exchanged between two voltage levels dictated by a blend of information signals. The utilization of rationale entryways for combinational logic ordinarily decreases the cost of parts for counter circuits to a flat out least, so it remains a mainstream approach. The counter has 70 numbers of transistors. Keywords - Flip Flop; SSASPL; Up Counter.

Author - S. M. Turkane, A. K. Kureshi

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| Published on 2018-08-14
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