International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Feb. 2024
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 131
Paper Published : 1705
No. of Authors : 4719
  Journal Paper


Paper Title :
Design of CMOS Multistage High Gain Differential Amplifier using Cadence

Author :Shivani M Aderao, Sushmakejgir

Article Citation :Shivani M Aderao ,Sushmakejgir , (2018 ) " Design of CMOS Multistage High Gain Differential Amplifier using Cadence " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 50-53, Volume-6,Issue-6

Abstract : In this paper behavior of multiple energy storage elements of Op-amp is observed. Initially a two stage Op-amp is designed using CMOS technology in VLSI. Designed Op-Amp consists of differential amplifier & gain amplifier. The initial stage of differential amplifier removes the noise and only amplifies the actual signal. Since the amplified signal does not meet Op-amp requirements a gain amplifier is used for amplification. 2nd stage is a common source amplifier which is used to increase the gain. Keywords - Cadence gpdk090, gpdk180, Differential Amplifier, Common Source Amplifier, Current Mirror circuit.

Type : Research paper

Published : Volume-6,Issue-6


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