International Journal of Electrical, Electronics and Data Communication (IJEEDC)
eISSN:2320-2084 , pISSN:2321-2950
current issue
Volume-7,Issue-12  ( Dec, 2019 )
  1. Volume-7,Issue-11  ( Nov, 2019 )
  2. Volume-7,Issue-10  ( Oct, 2019 )
  3. Volume-7,Issue-9  ( Sep, 2019 )

Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
Design of CMOS Multistage High Gain Differential Amplifier using Cadence

In this paper behavior of multiple energy storage elements of Op-amp is observed. Initially a two stage Op-amp is designed using CMOS technology in VLSI. Designed Op-Amp consists of differential amplifier & gain amplifier. The initial stage of differential amplifier removes the noise and only amplifies the actual signal. Since the amplified signal does not meet Op-amp requirements a gain amplifier is used for amplification. 2nd stage is a common source amplifier which is used to increase the gain. Keywords - Cadence gpdk090, gpdk180, Differential Amplifier, Common Source Amplifier, Current Mirror circuit.

Author - Shivani M Aderao, Sushmakejgir

| PDF |
Viewed - 50
| Published on 2018-08-13
IRAJ Other Journals
IJEEDC updates
Volume-7,Issue-12(Dec,2019) Want to join us ? CLick here
The Conference World



Technical Editor, IJEEDC
Department of Journal and Publication
Plot no. 30, Dharma Vihar,
Khandagiri, Bhubaneswar, Odisha, India, 751030
Mob/Whatsapp: +91-9040435740