Paper Title :Design And Analysis Of Low Power Sts Pulse Triggered Flip-Flop Using 250nm CMOS Technology
Author :M.Srinivas, K.Babulu
Article Citation :M.Srinivas ,K.Babulu ,
(2014 ) " Design And Analysis Of Low Power Sts Pulse Triggered Flip-Flop Using 250nm CMOS Technology " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 86-90,
Volume-2,Issue-9
Abstract : In this paper, a comparison of existing Flip-Flop (FF) system with different parameters is reported. A New design
of Flip-Flop has been proposed, having a structure of explicit pulse-triggered with a modified true single phase clock latch
based on signal feed through scheme. The post-layout simulation results using CMOS 250nm technology affirms that in the
proposed system delay is reduced when compared with existing systems. This Flip-Flop has a shorten delay which leads to
improve in speed and power saving too. Explicit Pulse-triggered Flip-Flop(FF), pulse signal can be shared to other Flip-Flop.
In the Proposed FF scheme not only the delay but also the power delay product, a true metric for comparison is optimized.
Type : Research paper
Published : Volume-2,Issue-9
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-1251
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Copyright: © Institute of Research and Journals
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Published on 2014-09-08 |
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