International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Nov. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 115
Paper Published : 1589
No. of Authors : 4352
  Journal Paper


Paper Title :
Reusable And Reconfigurable Approach To Functional Verification Of A Chip

Author :S. Madhuri

Article Citation :S. Madhuri , (2014 ) " Reusable And Reconfigurable Approach To Functional Verification Of A Chip " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 31-33, Volume-2,Issue-9

Abstract : Verification is a process used to demonstrate the functional correctness of a design. Also called logic verification or simulation. This paper demonstrates the functional verification planning process for creating a reusing and reconfigurable verification systems (test bench) which can be used to verify different versions of a component design with minimum changes in the verification environment by using minimum components for creating verification environment.

Type : Research paper

Published : Volume-2,Issue-9


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