International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Volume-7,Issue-12  ( Dec, 2019 )
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Statistics report
Feb. 2020
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 84
Paper Published : 1397
No. of Authors : 3784
  Journal Paper

Paper Title
Design and Implementation of High Speed and Energy Efficient Digital Circuit using Adaptive Logic

Abstract
Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. Reducing voltage in the circuit results in slow operation that incurs more delay. Canary circuits have been designed for error detection and error correction approach. Canary circuit results in large delay. Adaptive logic has been designed with dual latch phase in each stage. A combination of XNOR gate and flip-flop around each stage is added for the verification of correct operation. The entire architecture was modeled using Verilog code with the help of XILINX ISE tool . Index Terms - Timing margin, TED (Timing Error Detection), TEP (Timing Error Prevention), canary circuit.


Author - S.S.L.Ch.Mounika, K. Babulu

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| Published on 2018-01-27
   
   
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