10 Bit 500 MHZ Current Steering DAC
In this paper 10bit, 500M segmented current steering Digital to Analog converter is designed. The DAC is
implemented using 90nm technology with a supply voltage of 1.2V.The design is implemented with the matching network,
required for the current sources. Segmented architecture of the DAC is used in order to decrease the glitch and to improve
the Monotoncity, even though that increases the cost. The spurious free dynamic range (SFDR) and signal to noise and
distortion ratio (SNDR) performance of the segmented DAC architecture is also analyzed in this paper.
Index Terms- Segmented architecture, Monotoncity, Spurious free dynamic range (SFDR), Signal to noise ratio (SNDR)